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Altera_Forum
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14 years ago

DDR2 SDRAM Controller with ALTMEMPHY Synthesis error

Hi, I am trying to generate a DDR2 SDRAM Controller for a single 128 MB DDR2 chip. QSYS perform a good generation (6 warning wich don't concern the ddr2 Controller) but when i try to synthesis ...
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Altera_Forum
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14 years ago

I switched from QSYS to SOPC and the error message dissappeared.

I'm now once again trying to use QSYS (with Quartus2 version 11.0sp1) and the error message is still hanging in there.

After submitting a service request I got a reply saying something about toplevel signals not being declared correctly and therefore the signals not being mapped from the toplevel to the "2nd layer" (which is strange since designs using SOPC are compiling without the error message). Apparently some of the std_logic signals need to be declared as std_logic_vector(0 downto 0).

I tryed making changes in my toplevel file, however, the cryptic error message still persists. I'm looking further into this and will let you know if I find a solution.

regards saber890