Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

DDR2 SDRAM Controller with ALTMEMPHY Synthesis error

Hi, I am trying to generate a DDR2 SDRAM Controller for a single 128 MB DDR2 chip. QSYS perform a good generation (6 warning wich don't concern the ddr2 Controller) but when i try to synthesis ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

hi,

I created my first QSYS system today which I intend to implement on the Cyclone 3 development board.

I'm also getting the same error when trying to compile the system in Quartus2:

...ddr_clk_out_p|ddio_bidir_n5h:auto_generated|ddio_ outa[0]" must drive input port I of an I/O OBUF primitive

and also I have exactly the same warnings as you.

"in qsys i have connected soft_reset_n and global_reset_n inputs of the ddr2 controller to the clk_reset ouput of the clock source (wich also drive the reset_n input of the nios2)."

I have my system configured the same way.

Did you have any luck with solving the issue ?

regards Saber890