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Altera_Forum
Honored Contributor
17 years agoDDR2 reading errors on last two words
Hi, I've some problems with my ddr2 design. I use Altera DDR2 high performance IP on pci express dev board (Stratix II GX). I build some logic around my memory controler in order to test...
Altera_Forum
Honored Contributor
17 years agoActually, no timing erros with or without signal tap.
But after checking example driver results, something is not clear for me. does the pnf output need to be at '1' or at '0' to indicate good comparison ? Because in my case, pnf output is always at low level. And pnf_per_byte outputs are all low when writing and all high when reading. Except sometimes where some bits are low when reading! Well, I join two screenshots in order to help you to visualize example driver behaviour. Maybe it will be usefull for you. If the problem comes from my settings, I don't understand. Because I met all recommandations from altera (with the AN328). All timing requirements are good too. Maybe can you tell me more precisly which settings can cause this kind of fault ? (drive strength, output load, clock phase of pll...). I thank to you for all your help!