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This totally sounds like what I mentioned here:
http://alteraforum.com/forum/showpost.php?p=21095&postcount=9 --- Quote End ---
Right - it's as if the controller thinks that the memory is twice as wide as it actually is - but the settings look correct.
It's a half rate controller. The DDR bus is 64 bits + ECC (8 bytes)
The local bus is 256 bits (32 bytes).
Thus, every incrementation of local_address by 1 ( 1*32 = 32) should increment the DDR address by 4 ( 4 * 8 = 32)
Instead, the DDR address is being incremented by 8 - and then it's running out of column addresses.
Also, about your post:
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... the address locations you can access are only multiples of the data width.
For example, a 64-bit data width, addressing can only happen at these addresses : 0x0, 0x64, 0x128, 0x192, 0x256...etc
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You can only address locations that are multiples of the data width IN BYTES, so a 64 bit address bus can only address every 0x8 bytes, not every 0x64, because the addresses are byte aligned, not bit aligned. Also, the hex nomenclature 0x64 would actually be every 100 addresses decimal. Every 64 decimal bytes would actually be addresses every 0x40 hexidecimal bytes.
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