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Hi
I create a DDR2 High Performance Controller V7.1 with a stratix II device and find that the auto-generated SDC file include many constraints, such as DQ/DQS/Addr/Cmd output delay, DQ input delay, clock max delay, false path,etc. But When I create the same controller with a stratix III device, the auto-generated SDC file doesn't include DQ/DQS output delay, DQ input delay, clock max delay. It only includes Addr/Cmd output delay and less false paths. I have two questions:
1. Why there are so many differences between stratix II and stratix III?
2. Should I add the DQ/DQS output delay and DQ input delay and the others into SDC file when I use TimeQuest to analyze timing with DDR2 High Performance Controller in stratix III?
If someone knows about it, please tell me.
Thanks
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HI shsong ,
can you provide your ddr2 controller sdc file for reference?
regards
--sampath
Honored Contributor
