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Honored Contributor
Honored ContributorDDR2 Ctrl compile error:areset signal must be configures as clear but now as none
I have use the MegaWizard to generate the DDR2 sdram controller V7.2, and compiled it successful seperately, but when I intergrate it in my own design,there is a compile error: I/O atom "dqs" ddr_dqs...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Common causes of this are things like 1) Half (or more) of the local data bus is not connected … most likely the read. 2) Core requires a dedicated resynch clock and one has not been wired up 3) Read request is tied low. 4) Add constraints has not been applied --- Quote End --- It seems not because of the "common cause", what i design is under Quartus 7.2 and used the core DDR2/DDR sdram V7.2, there is no need a dedicated resynch clock ,and all of the local data bus is completed connected,but it still report that error, i have no idea how this happend!
