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nome's avatar
nome
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

DDR2 clock from PLL out

hello I am using Arria ii gx FPGA in Nios processor.altmemphy IP and our board main clock is 50 mhz i want to know about interfacing between DDR2 clock to FPGA my customize board connected the DD...
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EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,


Do you have any further update?


nome's avatar
nome
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hello

Thanks for your Comments

Warning (15899): PLL "nios_cpu:inst0_nios_cpu|lms_ctr:lms_ctr_inst0|lms_ctr_ddr2_1:ddr2_1|lms_ctr_ddr2_1_controller_phy:lms_ctr_ddr2_1_controller_phy_inst|lms_ctr_ddr2_1_phy:lms_ctr_ddr2_1_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy:lms_ctr_ddr2_1_phy_alt_mem_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy_clk_reset:clk|lms_ctr_ddr2_1_phy_alt_mem_phy_pll:half_rate.pll|altpll:altpll_component|altpll_mto3:auto_generated|pll1" has parameters clk2_multiply_by and clk2_divide_by specified but port CLK[2] is not connected


Warning (15899): PLL "nios_cpu:inst0_nios_cpu|lms_ctr:lms_ctr_inst0|lms_ctr_pll_0:pll_0|lms_ctr_pll_0_altpll_ecm2:sd1|pll7" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected

I am not understand why these above warnings occurs?

Thanks

Nome