Forum Discussion

nome's avatar
nome
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

DDR2 clock from PLL out

hello I am using Arria ii gx FPGA in Nios processor.altmemphy IP and our board main clock is 50 mhz i want to know about interfacing between DDR2 clock to FPGA my customize board connected the DD...
Memory
EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,


From your Quartus error and the "node name" in Pin Planner it is seem to be mismatch, please check the exact clock name in your that is defined in your top_level.v or top_level.qsys. That clock name should be the clock pin that you assign the PIN_F17. in Pin Planner.


FYI, I will be out until Christmas, and I will get back to you when I am back. We apologies for the inconvenience, I appreciate your patience.


  • nome's avatar
    nome
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Hello,

    Thank you for your reply.

    I have checked many times, and the "node name" and PIN_17 has the exact same name because SPI and UART in the Nios ii processor are working perfectly.

    However, whenever I add the PLL output connected to the DDR2 IP clock, critical warnings occur.

    Thanks, Nome