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nome's avatar
nome
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

DDR2 clock from PLL out

hello I am using Arria ii gx FPGA in Nios processor.altmemphy IP and our board main clock is 50 mhz i want to know about interfacing between DDR2 clock to FPGA my customize board connected the DD...
Memory
EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,


You need to locate the CLK[2] in your Pin Planner in Quartus, then assign that pin to location based on your schematics' Clock Pin.


  • nome's avatar
    nome
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Hello,

    Thanks for your reply.

    The main 50MHz clock for the Arria II GX FPGA is fed from pin F17. The pin specification in the Pin Planner designates it as a dedicated clock, CLK 14, and Diffclk_4n.

    My question is, how do I assign CLK[14] instead of CLK[2]?

    please find attachment

    Thanks

    Nome