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nome's avatar
nome
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

DDR2 clock from PLL out

hello I am using Arria ii gx FPGA in Nios processor.altmemphy IP and our board main clock is 50 mhz i want to know about interfacing between DDR2 clock to FPGA my customize board connected the DD...
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nome's avatar
nome
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hello

How to remove this warnings !

Warning (15899): PLL "nios_cpu:inst0_nios_cpu|lms_ctr:lms_ctr_inst0|lms_ctr_pll_0:pll_0|lms_ctr_pll_0_altpll_sgc2:sd1|pll7" has parameters clk2_multiply_by and clk2_divide_by specified but port CLK[2] is not connected

Thanks

Nome