DDR2 clock from PLL out

Hello.

Thanks for your reply.

Not helpful .....!

My simple question is: which PLL out for DDR2 differential clock do I have to use? In our case, the Arria II GX is using pin AJ16 and AJ15 for the

DDR2 clock and assigning PLL C0 and FPGA main clock is 50mhz and PLL C0 100mhz DDR IP Refclk.

during compilation critical warnings occurring

Warning(15899): PLL"nios_cpu:inst0_nios_cpu|lms_ctr:lms_ctr_inst0|lms_ctr_ddr2_1:ddr2_1|lms_ctr_ddr2_1_controller_phy:lms_ctr_ddr2_1_controller_phy_inst|lms_ctr_ddr2_1_phy:lms_ctr_ddr2_1_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy:lms_ctr_ddr2_1_phy_alt_mem_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy_clk_reset:clk|lms_ctr_ddr2_1_phy_alt_mem_phy_pll:half_rate.pll|altpll:altpll_component|altpll_mto3:auto_generated|pll1" has parameters clk2_multiply_by and clk2_divide_by specified but port CLK[2] is not connected

how possible assign? In SDC file

please help us

Thanks