Forum Discussion
kwkprd
New Contributor
3 years agoDDR Timing violations
Timing violation in task:- Report DDR timing analyzer
setup hold Address/Command (Fast 900mV 0C Model) | 0.18 0.18 Core (Fast 900mV 0C Model) | 1.391 0.012 Core Recovery/Removal (Fast ...
AdzimZM_Altera
Regular Contributor
3 years agoHello,
Are you using an Design Example generated from Quartus? Is there any other IP in the design?
What are the changes that you have made? It is possible that you share the changes again?
Regards,
Adzim