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kwkprd's avatar
kwkprd
Icon for New Contributor rankNew Contributor
3 years ago

DDR Timing violations

Timing violation in task:- Report DDR timing analyzer setup hold Address/Command (Fast 900mV 0C Model) | 0.18 0.18 Core (Fast 900mV 0C Model) | 1.391 0.012 Core Recovery/Removal (Fast ...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hello,


I have replicated the issue at my end and I can see the Read Capture timing violation with your EMIF IP setting.

I may suggest to use faster memory component that compatible with your memory device.

From my end, I have used memory speed bin -3200 parameter setting and running at 1066.667MHz clock frequency.

The timing is clean after running the compilation.

I hope you can get a same result as well.


Regards,

Adzim