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Altera_Forum
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18 years ago

DDR SDRAM controller Compilations error in Cyclone III

Hi I am trying to build a project with a Nios II/f processor and a DDR SDRAM interface on a Cyclone III FPGA. I have used the preset for the Micron MT46V14M16TG. The controller can only r...
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Altera_Forum
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18 years ago

I have fixed the last error by changing , to . in all numbers in the file (I wonder why the file is generated with , in the numbers ????), but I still get the first error. If I comment out the line then I can compile the design, but the deign does not work in the FPGA.

The line I comment out is:

sett_collection c [get_pins -compatibility_mode $measure_pattern]

Does anybody know what the problem is in this line and do I need it or can I comment it out?

I do not know if I should file an error report to Altera or if it is my own fault that I get all these problems.

Regards

Tom