Forum Discussion
11 Replies
- Altera_Forum
Honored Contributor
the output latency of usedw depends on parameter settings. It can be more than one rd- or wr-clock. Please refer SCFIFO and DCFIFO IP Cores User Guide.
HI,
Im using a DCFIFO (dual clock fifo) to transfer clock domains. i genreated a DCFIFO, but i get timing violations from 1 clock to the other regards Fifo components. should i "set_flase_path" for all clock_A to clock_B paths (the clock are not related)?the output latency of usedw depends on parameter settings. It can be more than one rd- or wr-clock. Please refer SCFIFO and DCFIFO IP Cores User Guide.