Forum Discussion
ContributorDCFIFO not empty but rdusedw=0 ?! (Agilex)
I'm just going by what I think is the most recent version of the guide:
https://www.intel.com/content/www/us/en/docs/programmable/683522/18-0/fifo-user-guide.html
Looking through it, I see the add_usedw_msb_bit option, which might be what you're looking for to see the correct value on rdusedw and wrusedw.
I don't know why the read side is showing empty when wrfull indicates it's full (which is strange), but check out the latest version of the guide and see if that helps. You're looking at a 12 year old version of the doc.
Super ContributorI'm just going by what I think is the most recent version of the guide:
https://www.intel.com/content/www/us/en/docs/programmable/683522/18-0/fifo-user-guide.html
Looking through it, I see the add_usedw_msb_bit option, which might be what you're looking for to see the correct value on rdusedw and wrusedw.
I don't know why the read side is showing empty when wrfull indicates it's full (which is strange), but check out the latest version of the guide and see if that helps. You're looking at a 12 year old version of the doc.
ContributorGood catch, indeed I used an old documentation because the formula isn't present in the new one.
It's just crazy that it rolls over to zero per design... I really thought we were done with such mistakes after the Ariane 5 rocket crash due to an overflow.
Fascinating, instead of fixing the IP for good and make it consistent, let's add a parameter as a workaround.
Thanks!
edit:
Actually the lpm_numwords' formula was changed in the new one, it's even more restrictive:
The value assigned must comply to the following equation: 2^LPM_WIDTHU
