Forum Discussion
ContributorDCFIFO not empty but rdusedw=0 ?! (Agilex)
I'm just going by what I think is the most recent version of the guide:
https://www.intel.com/content/www/us/en/docs/programmable/683522/18-0/fifo-user-guide.html
Looking through it, I see the add_usedw_msb_bit option, which might be what you're looking for to see the correct value on rdusedw and wrusedw.
I don't know why the read side is showing empty when wrfull indicates it's full (which is strange), but check out the latest version of the guide and see if that helps. You're looking at a 12 year old version of the doc.
ContributorSorry about that, I edited the question, my device is Agilex.
The screenshot represents a steady state, anything timing related between the full signal and the wrusedw is irrelevant. The wrusedw is still wrong.
There are other cases we want to know the number of words inside the FIFO. I, of course, use the full signal to trigger correct write operations.
wrfull is your "6th bit" That's quite an unacceptable workaround and I really don't understand how this kind of weird inconsistency design can be approved by an engineer.
Xilinx has been smarter with their XPM IPs and shows consistency by adding 1b width to the counter to always show the correct value.
How about the read side? rdusedw is actually the one I really use. Which signal becomes my 6th bit?
Why does it show it non-empty with 0 data in? (again, with the fifo being full at the same time and in a steady state)
Thank you for trying to help me but convincing me the inconsistent design and flaws are normal is a lost cause.
