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alexislms's avatar
alexislms
Icon for Contributor rankContributor
4 years ago
Solved

DCFIFO not empty but rdusedw=0 ?! (Agilex)

I had the unpleasant surprise to see a FIFO being full with 0 word, and being not empty with 0word inserted. Possible cause: For lpm_numwords=32, I set lpm_widthu to be 6. Neverthe...
  • sstrell's avatar
    sstrell
    4 years ago

    I'm just going by what I think is the most recent version of the guide:

    https://www.intel.com/content/www/us/en/docs/programmable/683522/18-0/fifo-user-guide.html

    Looking through it, I see the add_usedw_msb_bit option, which might be what you're looking for to see the correct value on rdusedw and wrusedw.

    I don't know why the read side is showing empty when wrfull indicates it's full (which is strange), but check out the latest version of the guide and see if that helps. You're looking at a 12 year old version of the doc.

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
4 years ago

You don't specify which device you're using, but the DCFIFO guide (v18.0) says this in the signal table for wrusedw:

"For Stratix, Stratix GX, and Cyclone devices, the FIFO Intel FPGA IP core shows full even before the number of words stored reaches its maximum value. Therefore, you must always refer to the full or wrfull port for valid write request operation, and the empty or rdempty port for valid read request operation regardless of the target device."

So I guess you only need 5 bits of wrusedw because when you get to 32, wrfull goes high and wrusedw goes back to 0. wrfull is your "6th bit".