alexislms
Contributor
ContributorDCFIFO not empty but rdusedw=0 ?! (Agilex)
I had the unpleasant surprise to see a FIFO being full with 0 word, and being not empty with 0word inserted.
Possible cause:
For lpm_numwords=32, I set lpm_widthu to be 6. Neverthe...
I'm just going by what I think is the most recent version of the guide:
https://www.intel.com/content/www/us/en/docs/programmable/683522/18-0/fifo-user-guide.html
Looking through it, I see the add_usedw_msb_bit option, which might be what you're looking for to see the correct value on rdusedw and wrusedw.
I don't know why the read side is showing empty when wrfull indicates it's full (which is strange), but check out the latest version of the guide and see if that helps. You're looking at a 12 year old version of the doc.
