Forum Discussion
Altera_Forum
Honored Contributor
13 years agoi've the attached the waveform and here the test-bench code
`timescale 1ps/1ps
module tb_dc_fifo();
reg wr_clk, rst, rd_clk;
reg data;
reg rdreq, wrreq;
wire q, data_out;
wire rdempty, rdreq_o;
initial
begin
wr_clk = 1'b0;
rd_clk = 1'b0;
data =45'h0AAAAAAAAAAA;
rst = 1'b1;# 45 rst = 1'b0;
rdreq = 1'b0;
wrreq = 1'b1;
end
always# 100 wr_clk = ~wr_clk;
always# 5 rd_clk = ~rd_clk;
//---------------FIFO INSTANTIATION-------------------
fifo_new fifo_new_inst (
.data ( data ),
.rdclk ( rd_clk ),
.rdreq ( rdreq_o),
.wrclk ( wr_clk ),
.wrreq ( 1'b1 ),
.q ( q ),
.rdempty ( rdempty )
);
//-------------READ LOGIC MODULE INSTANTIATION--------
read_control_logic read_control_logic_inst(
.rst(rst),
.rdclk(rd_clk),
.rdempty(rdempty),
.rdreq(rdreq_o),
.q_read(q),
.dataout(data_out)
);
endmodule
Any help will be much appreciated!!