Data stream to PCIe: regular or scatter gather DMA controller?

The regular DMA uses memory mapped interfaces, which are designed to be connected to memory components, or at least components with an area mapped as a memory. Of course you can choose to emulate a memory component by ignoring the address and connect some signals as you are trying to do, but there are several problems:

[list][*]as a general design rule, you shouldn't use a generated signal as a clock in an FPGA. You can have glitches on that signal, that can cause unwanted clock cycles at unpredictable times (and usually not when you want them ;) ) and timing problems

[*]if the DMA wants to read on several cycles in a row it will just keep the read_n signal low. So if you use it as a clock it won't work. Instead, use the same clock the DMA is using as the fifo read clock, and use an inverted version of read_n for the read request.

[*]by keeping the wait request always low you won't prevent the DMA from trying to read your fifo when it is empty. You should probably use this signal to stop the DMA when the FIFO is empty instead

[*]keeping the data valid signal high violates the specification (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf) which says "A slave with readdatavalid must assert this signal for one cycle for each read access it has received. There must be at least one cycle of latency between acceptance of the read and assertion of readdatavalid." It may or may not work with the DMA controller (I don't know its internals) and even if it does there is no guarantee it will work with future versions. It is better to stick to the specification and use for example a delayed version of the read request.

[*]as you don't decode the address you have no way of knowing where the controller is in its transaction. Depending on the type of data you need to transfer it may not be a problem, but in some cases it can be interesting to signal the beginning and the end of a transaction, for example because you are sending packets with a specific format, or you need to keep track of timing. You could read the address to detect when you are at the beginning of a transaction, but you have no way to tell the DMA controller that the transaction is finished.[/list]

The Avalon Stream interface is more adapted to those kind of transfers IMHO, and it very easy to use.