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Altera_Forum
Honored Contributor
13 years agoI don't understand what it means when you say that the regular dma can only do memory to memory transfers and one of the others is required for using fifos. Is that just more efficient or am I missing something fundamental in the interface fabric?
For a simple case, which is what I'm trying to get working now, can I not connect a fifo to exported signals from the regular dma read master as follows: read_n signal from the dma port to the fifo read clock fifo data out to dma read data in dma read wait request always low dma read data valid always high