osi-hw
New Contributor
3 years agoCyclone V with RapidIO ip core
Hi,
I want to simulate Rapidio passthrough avalont Streaming on cyclone V (Questasim) but I do not manage to have a link between the first rapidio (instance A) and the sister rapidio (instance B)....
- 3 years ago
Hi,
Please refer these Cyclone V Rapid IO example design.
https://community.intel.com/t5/FPGA-Wiki/RapidIO-Example-Design/ta-p/736028
and also please refer the debug checklist as well.
https://community.intel.com/t5/FPGA-Wiki/RapidIO-Gen1-Debug-Checklist/ta-p/736030
Thank you
Kshitij Goel