Forum Discussion
osi-hw
New Contributor
New ContributorCyclone V with RapidIO ip core
Hi,
I want to simulate Rapidio passthrough avalont Streaming on cyclone V (Questasim) but I do not manage to have a link between the first rapidio (instance A) and the sister rapidio (instance B)....
Hi,
Please refer these Cyclone V Rapid IO example design.
https://community.intel.com/t5/FPGA-Wiki/RapidIO-Example-Design/ta-p/736028
and also please refer the debug checklist as well.
https://community.intel.com/t5/FPGA-Wiki/RapidIO-Gen1-Debug-Checklist/ta-p/736030
Thank you
Kshitij Goel
Kshitij_Intel
Frequent Contributor
Frequent ContributorHi,
As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
Thank you
Kshitij Goel
