Forum Discussion
osi-hw
New Contributor
New ContributorCyclone V with RapidIO ip core
Hi,
I want to simulate Rapidio passthrough avalont Streaming on cyclone V (Questasim) but I do not manage to have a link between the first rapidio (instance A) and the sister rapidio (instance B)....
Hi,
Please refer these Cyclone V Rapid IO example design.
https://community.intel.com/t5/FPGA-Wiki/RapidIO-Example-Design/ta-p/736028
and also please refer the debug checklist as well.
https://community.intel.com/t5/FPGA-Wiki/RapidIO-Gen1-Debug-Checklist/ta-p/736030
Thank you
Kshitij Goel
Kshitij_Intel
Frequent Contributor
Frequent ContributorHi,
Can you please generate the simulation model for the RapidIO II IP Core and run the testbench.
Also, you can refer to the reference design as well.
Hope this will resolve your issue.
Thank you
Kshitij Goel
osi-hwHi Thank you for your reply.
The link you sent me is amreafy on my first comment.
When I run the simulation for the stratix 10 which is the device ised on the reference design. everything works fine.
But when I reproduce this design for the cyclone V it does not work because it is not the same family and not the same ip core.
so no it does not solve the issue.
Best Regards.
