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BAbbott's avatar
BAbbott
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4 years ago

Cyclone V SX - dual 10Gbe XAUI

Hi,

I'm looking into implementing a dual XAUI interface for 10Gbe ethernet using the XAUI IP in a Cylcone V SX (5CSXFC5). I've been able to implement one, but I'm having issues implementing two. Theoritically, is it possible to implement two using the 9 GXB transceivers (Lanes 0-3 and Lanes 5-8) or do I need to go a different route?

It also looks as though 10Gbe is the only option - should I be using the 156Mhz reference clock for the REFCLK pins for this implementation or can they run to global clock input pins?

5 Replies

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Besides, you have to use the 156.25Mhz as the input reference clock frequency for the XAUI.


    • BAbbott's avatar
      BAbbott
      Icon for New Contributor rankNew Contributor
      4 years ago

      So using CH4 for the input PLL + CH5-8 as the interface should be sufficient with REF_CLK0 being the input for the 156.25MHz?

      Making sure I understand that correctly.

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,


    This is suggested to compile with a simple design to see if the Quartus allow this kind of combination to fit and whether there is any critical warning.




  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

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