Cyclone V GX Dev Board DDR3 Timing Violations

My next step in the process was to do a full compilation. To my surprise, and a half hour later, my design was full of more timing violations. This time, mostly setup violations. I again went to the Timequest timing analyzer, created a netlist (post-fit), and repeated my procedure of adding commands to my sdc file. This time, I added mostly "set_max_delay" to the clock signals that were showing setup timing violations. After fixing the timing violations, again, I did a full compilation. This time it compiled with no violations.

I still feel totally insecure with the design I have built. The compilation says I have 8 critical warnings, and 178 other warnings, but compilation was a success.?! I get .sdc file warnings about clocks that could not be matched with a clocks, ignored set false paths, overwriting existing clocks, ignored set_clock_uncertainty, things that could not be matched with a pin, empty collections, the fitter compensating PLL clocks, dqs assigned different I/O standards, and a ton of other stuff I have no idea what is means. Sometimes I look up the errors and I find that the Altera knowledge base says I can ignore these warnings. Really?

Altera - com' on man! Make this better.