Cyclone V Avalon-MM Interface for PCIe Root Port Questions

You can use custom logic or the NIOS/HPS on the FPGA to act as the bus master in your design. The only thing you need to make sure is that it is accessible via firmware/software. As I mentioned before, the RC cannot perform the configuration, data transfer on its own. It needs the help of the firmware/drivers and application software to do so. When the system is powered on, the firmware will ensure that the RC is enumerated / detected , BARs configured . The next step is for the firmware to start the PCIe discovery process and also the link training and configuration for the downstream EPs. Once the RC responds back to the firmware with a list of EPs downstream and the configuration is done, the firmware hands control to the application software which then starts/initiates the data transfer.

When you implement the RC/EP you will have to specify how many BARs you want to use and its address range. The BARs have its own configuration and parameters that need to be set. Once you have set these parameters and configured the RC/EP IP, you can generate the IP and connect it to the rest of the design.

Thus when the firmware is configuring the RC/EP, it will try to write a series of 1's to the BARs and wait for a response from the RC/EP. Once it gets the required response with the data, it will know the BAR details of the PCIe device being configured, its memory mapping, range, device ID, vendor ID, capabilities, max payload, etc.