Cyclone V Avalon-MM Interface for PCIe Root Port Questions

Thank you for your reply, Abraham. I think that I understand most of that, but I have some more specific questions.

The reason that my questions are more specific is because I am not planning on using the processor, but using FPGA fabric/firmware/custom logic to do the "processor"/bus mastering functions that you speak of.

I'm assuming that the processor performs bus enumeration by submitting Configuration TLPs. How is this accomplished? Through the root port TLP data registers or can this be done through the Avalon-MM Txs slave interface? If it can be done through the Txs interface, what is the format of the data necessary and what address should be used?

Once bus enumeration is performed, how do you map a bus, device, function, and/or BAR space to the Avalon-MM Txs slave address for sending Memory Read/Write TLP data? What is the format of the data (e.g. do you need to supply the TLP header along with the TLP data/payload, or do you just need to supply the TLP data/payload)?

Thanks again, in advance.