Cyclone V - major transceiver misunderstanding

Hi,

I was able to succesfully implement the word alignemnt in my simulation project (yes, I went from Signal Tap to simulation.....).

I started (as suggested) by implementing an 8 bit word transmission, went to 16 bit and now, I have my 32 bit word transmission with bit slipping word alignment running.

I thought, that now I am able to just start the transmission of my user data in between the 32 bit sequence I use for word alignment.

In order to test this, I started to transmit increasing counter values that initially starts at 0x0e0f0000. So I am able to see if all 32 bits are transferred correctly.

so the sequence would be

0x0e0f0000

0x0e0f0001

0x0e0f0002

0x0e0f0003

0x0e0f0004

0x0e0f0005

.....

So the complete data stream I provide to the tx side is like this:

......

0xaa5533ff

0xaa5533ff |

0xaa5533ff |

0xaa5533ff > used during word alignemnt with bit slipping

0xaa5533ff |

0xaa5533ff |

0xaa5533ff / <----- word alignment on rx side finished, pattern on RX received as send by TX.

0x0e0f0000 <---- Counter Squence starts on TX side.

0x0e0f0001

0x0e0f0002

0x0e0f0003

0x0e0f0004

0x0e0f0005

.....

Now, the problem is that in between the succesfull word alignment and the first correctly received counter pattern word, I get something like this on the RX side:

0xf54a533f

0xf54aa67f |

0xea95a67f |

0xea954cff > word alignemnt with bitslipping on RX side

0xd52a4cff |

0xd52a99ff |

0xaa5533ff / <--- word alignment pattern found, bit slipping stopped

0x0e0f33ff <----- would have expected that I receive the 32 bit counter sequence put into the TX side. Where is this pattern coming from?

0x0e0f0000 <----- from here on, everything seems to be correct

0x0e0f0001

0x0e0f0002

0x0e0f0003

....

So, I hope you see what my problem is and what the question will be: How can I avoid this "additional"(???) data? Do I need something like "byte ordering"?. If yes, why would I need this?

My (mis-)understanding is that I must be fine after word alignment is finished sucessfully because the parallel data I send on the TX side is serialized, received on the rx side, bit slipped into the correct word boundaries and that's it. If no more bit slipping is aplied, the serialized data stream from the TX side should just come ot of the parallel rx side in the correct manner.

The next thing is, that I don't really understand the importance of byte ordering (especially in this case). Can somebody explain, why it would be necessarry? I've read the Altera documentation and have seen the examples, but with my explanation from above I don't see the reason for byte ordering once the word alignment hase been successfully performed.

I attached the modelsim waveform which shoes the word alignment process. The marker is placed at the questionable data word reception. (by the way, maybe somebody can answer why the tx_ready and rx_ready signals become 'X' once they should be '1'....)

Edit: Okay, I think, maybe I have also a missunderstanding in the way, a 32 bit word is transferred over the transceiver link.

What I have:

32 bit parallel data port FPGA fabric ransceiver interface width.

16 bit PCS-PMA interface width.

I read in the documentation that the least significant 16 bit word (LSBW) of my 32 bit user data is transmitted first and after that the most significant 16 bit word (MSBW) of my 32 bit user data is transferred. Because of this, I suppose that the TX-LSBW ends up in the RX-MSBW and the TX-MSBW goes into the RX-LSBW. Is that assumption correct?

I think, it has to be that way, because otherwise (TX-LSBW -> RX-LSBW, TX-MSBW -> RX-MSBW), I was not able to get mey word alignment correct with bitslipping.

Now, I wonder if maybe I have an error already here because when I send user data, it appears that I always have MSBW of the next 32bit value mixed up with the LSBW of the currently expected 32bit data word.

Again, I have the question, if there is a very simple example available, where I can just put in 32 bit user data on one side and get the same 32 bit data out of the other side. I'm really struggeling a lot and can just not figure out how this would work for the very simple transmission I want to realize.....

Thanks,

Maik