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Honored Contributor
Honored ContributorCyclone V - DDR3 UniPHY memory controller example design synthesis error
Hi folks, I was trying to add a DDR3 UniPHY memory controller example design into an existing project, but I always get the same error message when I run analysis & synthesis: error (17044...
Altera_ForumHonored Contributor
Honored ContributorI have reported this problem to the "Altera Service Request online" without no feedback for a month!
"error (17044): illegal connection found on i/o input buffer primitive ...also drives out to other destination than the buffer." Maybe you can try the altmemphy IP core in your project!
