Honored Contributor
Honored ContributorI used google translator:
" I recently did ddr2 memory in this design, fgpa chip model EP4CGX15, DDR2 choices are Micron Technology MT47H32M16CC chip, due to less fpga chip pin, connect to DDR2 BANK uses a total of five BANK3-BANK7 BANK, which controller clock is 148.5MHz, fpga maximum frequency of 167MHz, functional simulation has been achieved, but next to the board but does not work. We listed the following specific problems: 1. Compile, but there are warning timing, timing constraints on the design done, the problem still exists. 2. With 10.0, 10.1, 11.0 ip customized version of the nuclear, but not to adopt the logic analyzer data, init_d one is always low. Later, with the 9.1 version of the custom ip core, compiled in 5.0 above, the logic analyzer can be taken to the data, and init_done high, read and write operations, but not read out the data (the same has been read out of one or several number), not the number of control signals. Now want to consult your family have hung ddr2 in 15 successful cases. Distribution will not be too loose pin, the internal logic complexity resulting sequence alignment can not be met or for other reasons, look forward to your reply!" I was just curious what they were talking about. Cheers
