Cyclone 10 GX Transceiver Power-Up Calibration Time (~353 ms) Analysis Request

Below an update on the questions

could you please share with me how you are measuring the calibration time in your setup (for example, which signals you are monitoring and from which point to which point the time is measured)?

We use an internal Signal Tap with a 1 kHz clock (1 ms per tick). The measurement is triggered immediately after FPGA configuration is completed (Power-Up Trigger)

We track: ATX pll_lock, ATX cal_busy and rx_cal_busy and tx_cal_busy for each transceiver channel

We would like to focus specifically on SGMII (GbE) now, which is why the latest communication only addresses this case.

a ~353 ms calibration time would generally be considered expected behavior, rather than an anomaly.

Out of curiosity, how is it possible to meet the ~100 ms PCIe enumeration requirement if these calibration times are expected (especially without even considering FPGA configuration time)?

If you are currently using CLKUSR at 100 MHz, you may try increasing it to 125 MHz to see whether it helps reduce calibration time.

    In addition, please ensure that: CLKUSR and all reference clocks are stable and free‑running before FPGA configuration begins

Sure we can try increasing CLKUSR from 100 MHz to 125 MHz, although based on our current measurements we do not expect a significant improvement.

We have ensured that CLKUSR and all reference clocks are stable and free-running before FPGA configuration begins. Additionally:

We tested triggering a reconfiguration after sufficient time has elapsed (ensuring full system stability), and observed similar timing results.

We also repeated the test using a Cyclone 10GX Evaluation Kit (validated Altera hardware), and obtained comparable results.

Thank you