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ACamp22's avatar
ACamp22
Icon for New Contributor rankNew Contributor
5 years ago

Cyclone 10 DDR3 Address Pin assignment

Hello, we have a design with a Cyclone 10 GX, we are using a hard DDR3 controller. After an early pin placement, the PCB guys asked us to swap some pins (ddr_dq data, ddr_dm and ddr_a). no prob...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
5 years ago

For the hard memory controllers in Cyclone 10 GX, control signal locations (including address) are fixed in their designated I/O bank. They are not swappable. DQS and DM pins have limited swappability within their I/O lanes, so you may have gotten lucky there.

You can look at the "Read Me" for the IP to see the suggested placement and if there is anything you can swap. It is located in:

<project_directory>/<variation_name>/altera_emif_arch_nf_<Quartus_version>/synth/<unique_variation_name>_readme.txt

If you are using the Pro edition of Quartus, you can use the Interface Planner tool to select a legal location for the interface and then perform individual pin swaps. The tool checks on-the-fly if a swap is legal for the IP and generates a Tcl script you can run which will create all the correct legal pin location assignments.

For more detail on constraining a memory interface design, see this online training:

https://www.intel.com/content/www/us/en/programmable/support/training/course/omem1122.html