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brian1211's avatar
brian1211
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

CXL type 3 m2s_req and m2s_rwd message access?

Trying to use the R-Tile Intel FPGA IP for Compute Express Link (CXL) in the type 3 configuration and need to be able to interface at the the .mem interface, not use the AMM interface provided. Is t...
  • JonWay_C_Intel's avatar
    JonWay_C_Intel
    2 years ago

    Hi, as discussed in the meeting, the QHIP IP is expected to be available in the next release which exposes the memory interface.


JonWay_C_Intel's avatar
JonWay_C_Intel
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi, as discussed in the meeting, the QHIP IP is expected to be available in the next release which exposes the memory interface.