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RicardoC's avatar
RicardoC
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

CXL IP DVSEC

Hi, Is the PCIe DVSEC registers for CXL Device implemented either in the R-Tile CXL HIP or in the Soft Wrapper? If not, is there an Intel IP that can be attached to the CXL.IO port that can provide...
JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.