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RicardoC's avatar
RicardoC
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

CXL IP DVSEC

Hi, Is the PCIe DVSEC registers for CXL Device implemented either in the R-Tile CXL HIP or in the Soft Wrapper? If not, is there an Intel IP that can be attached to the CXL.IO port that can provide...
JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


Currently the IP you are using is not suitable and we are updating new IP in 23.1. For now, please use R-Tile Intel FPGA IP for Compute Express Link (CXL) IP.


  • RicardoC's avatar
    RicardoC
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Hi John,

    Will the the new IP in 23.1 have support for the CXL configuration and DVSEC registers?

    Thank you,

    Ricardo.