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RicardoC's avatar
RicardoC
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

CXL IP DVSEC

Hi, Is the PCIe DVSEC registers for CXL Device implemented either in the R-Tile CXL HIP or in the Soft Wrapper? If not, is there an Intel IP that can be attached to the CXL.IO port that can provide...
RicardoC's avatar
RicardoC
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Hi,

Instantiating the Intel R-Tile for Compute Express Link IP in Platform Designer gives me an option to choose the CXL Function Mode as:

-Full TLP Bypass

-Partial TLP Bypass

-Normal

If "Normal" is selected, a new tab appears with options to configure "CXL DVSEC Settings", "Device ID", "Vendor ID", capabilities, etc.

Can you clarify what the difference is between these 3 modes, and also if the above listed features under "Normal" are operational?

Thank you,

Ricardo.