Forum Discussion
RicardoC
Occasional Contributor
Occasional ContributorCXL IP DVSEC
Hi,
Is the PCIe DVSEC registers for CXL Device implemented either in the R-Tile CXL HIP or in the Soft Wrapper? If not, is there an Intel IP that can be attached to the CXL.IO port that can provide...
JohnT_Altera
Regular Contributor
Regular ContributorHi,
I am refering to the IP (R-tile Intel FPGA IP For Compute Express Link) that you are planning to used. If you look at the Figure 4, the IP will have the connection till HDM interface where user will be designing their own iAFU.
If you are using Intel R-tile for Compute Express Link then you will need to write your own CXL wrapper design. As it will only exported out CXL.IO, CXL.MEM and CXL.CACHE interface.
