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RicardoC's avatar
RicardoC
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

CXL IP DVSEC

Hi, Is the PCIe DVSEC registers for CXL Device implemented either in the R-Tile CXL HIP or in the Soft Wrapper? If not, is there an Intel IP that can be attached to the CXL.IO port that can provide...
JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi Ricardo,


If you are refering to CXL Type 3 implementation then the DVSEC will be fully soft-logic.


RicardoC's avatar
RicardoC
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Hi John,

Thanks for the information, but it seems that you are still referring to the Design Example. We would like to use the CXL IP for our own project and I would like to know if the DVSEC is implemented in the IP provided by Intel or if this has to be developed by customers.

Thank you,

Ricardo.