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RicardoC's avatar
RicardoC
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

CXL IP DVSEC

Hi, Is the PCIe DVSEC registers for CXL Device implemented either in the R-Tile CXL HIP or in the Soft Wrapper? If not, is there an Intel IP that can be attached to the CXL.IO port that can provide...
JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi Ricardo,


If you are refering to Figure 4 of CXL1.1 IP User Guide, yoyu will observed that the CXL.MEM and CXL.IO is implemented in soft logic. Only the PHY willbe on the Hard IP.


  • RicardoC's avatar
    RicardoC
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Hi John,

    Thank you for the feedback.

    We can use Figure 4 of the CXL IP User Guide as a reference, but I do not intend to use the Design Example in this project. I was wondering if the registers defined in the CXL spec and the appropriate surrounding logic is present when the CXL IP is generated in the platform designer.

    These are the PCIe DVSEC for CXL Device defined in the CXL spec:

    Thank you,

    Ricardo.