Occasional ContributorHi,
I have a few questions regarding the CXL IP in the 23.1 release.
1. Where can the R-Tile Compute Express Link FPGA IP User Guide for the 23.1 release be found?
2. Is there an updated version of the CXL Example Design User Guide?
3. Where can the testbench for the Example Design for the new Design type option "CXL Base Hard IP" be found?
Thank you,
Ricardo.
Regular ContributorHi,
We are still in the progress of finalizing the document. It should be schedule to be available in WW17. Sorry for the inconvennience.
Occasional ContributorHi John,
Thanks for the update.
Will the testbench for the Example Design also be available at the same time?
Thank you,
Ricardo.
Regular ContributorHi,
Yes, testbench will be available as well.
Regular ContributorHi,
Sure, will provide it once available.
Occasional ContributorHi John,
I just noticed that the 1.8 version of the CXL Example Design document was released 2 days ago. However, the link for the Base Hard IP testbench is the same of the DDR3 type (see page 45). Can you please provide the correct location of the Base Hard IP testbench (cxlbasehip_tb_23p1.zip)?
Thank you,
Ricardo.
Regular ContributorOccasional ContributorThank you.
New ContributorHi,
I'd like to download the testbench zip file with asset ID number 778342.
It seems the link no longer works.
I got this error message after clicking on that link:
Oops, something went wrong!
The page you requested has moved or doesn't exist. If you followed a link, it's probably broken - but don't worry, we've already reported it. In the meantime, why not take a look around?
Could someone @intel look into this issue?
Thanks,
-Brian
