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Raj_G's avatar
Raj_G
Icon for New Contributor rankNew Contributor
3 years ago

CXL Example Design simulation: Illegal combination of drivers

Hi, Running the simulation of the CXL Example Design, following the CXL_Reference_Designs_User_Guide_v1.5.pdf document, gives the following errors during elaboration: Error-[ICPD_INIT] Illegal co...
RicardoC's avatar
RicardoC
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hi John,

I downgraded the version of Verdi to 2019, as show in your elaboration log file, and this allowed the code to be compiled with the -kdb option enabled. The simulation runs longer than before, but it fails with:

UVM_ERROR /fpga/P-2019.06-SP2-6/cxltyp3ddr_tb_22p4/tb/tests/cxl_base_test_eot_checks.svhp(43) @ 593702.342ns: uvm_test_top [CXL_REPORT] CFG_CORERRSTS is 0x4001

I've attached the complete simulation log file for your reference.

Any recommendations?

Thank you,

Ricardo.