CXL Base Hard IP configuration

Hi,

I believe you mean R-Tile Intel® FPGA IP for Compute Express Link* (CXL) Design Example User Guide (https://cdrdv2.intel.com/v1/dl/getContent/763513).

That was not actually what I was looking for. Back when I asked the question, I wanted to know if and how the Base HIP could be configured to route CXL.mem requests/responses through the CPI bus, since the Base HIP Design Example strictly exercised CXL.cache traffic. I later realized that some of the changes would be on the Base Class Code, Sub Class Code, Programming Interface, etc.

Are there any other settings that should be modified to support CXL.mem in the Base HIP?

Thank you,

Ricardo.