Honored ContributorHi all,
I have a Custom IP developed in VHDL and i am able to communicate with the NiosII Soft processor.But when i simulate the Nios II processor,the communication between the Nios II and the IP is not as expected. If i watch the slave_write and chip_select ,then in between the consecutive slave_write pulses,there comes a slave_read pulse also. How to avoid the slave_read pulses in between?
Honored ContributorUsually, the slave write/read is controlled in the application code. You might want to check your code and see whether you have inserted the reads.
Honored ContributorI have checked the application code .I am only allowing two writes from the code.No read operation i am doing in between.
But when i simulate in modelsim,it shows a read signal in between the two write operation.Honored ContributorAre you using the io.h to perform IOWR_32DIRECT? Is Nios the only master to your custom IP?
Honored ContributorIs the write instruction writing a whole word, or only a partial word - ie is the processor reading the full word, modifying the data and then writing back the full word having left the top byte unchanged, or similar?
Honored ContributorHonored ContributorHonored ContributorDid you trace back the read to Nios?
What happens if you remove the writes from your application? What is your custom IP doing?
