Critical Warning (10169) on DDR2 ALTERA IP

I'm using Altera's DDR2 IP to control DDR2 memory. 2 critical warnings as below pops out after compilation. The warnings are pointing to the code that ALTERA provided for DDR2 control.

I don't konw why these 2 warnings pop up with "critical level". Should I do something to resolve these warnings and how? or just leave them as it is?

(The attachment is my project files)

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Critical Warning (10169): Verilog HDL warning at alt_mem_ddrx_controller.v(508): the port and data declarations for array port "afi_rrank" do not specify the same range for each dimension

Critical Warning (10169): Verilog HDL warning at alt_mem_ddrx_controller.v(509): the port and data declarations for array port "afi_wrank" do not specify the same range for each dimension

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