Honored Contributor
Honored Contributorwell, my plan was to use only a few address lines for configuration. Configuration data doesn't need much memory capacity.
The other address lines, I would use for fetching pictures out of the flash during user mode. So the FPGA thinks, there are two memories. Perhaps Pull-Downs aren't necessary, because of the tri-state status of the adress pins for the pictures during user mode. I don't know, if this is possible according to the locations of the addresses in the flash during configuration. Parallel configuration is necessary, because I need a very short configuration time.
