The first solution is easy. You only need your Nios (or any other processor) drives a spi master which is used to access SD. This for the SD physical layer: depending on how data is stored on your SD, you may need more or less effort in designing the applicaiton (i.e. file system management)
Clearly this solution involves a greater BOM cost, unless you already have a second processor external to the fpga and you can use it for the configuration task
The second solution would be more correct. I think what you choose depends on how much effort you want to put in the design. The initialization and basic access to SD is not that complicated, especially if you don't need to support all SD device variants. But in the CPLD solution you surely can't use a file system and must load the fpga configuration image as raw data in the SD flash eprom.