Compatibility

I've used the Fir in 7.2 and has no problem.

Try to have a look at the help.

Moreover:

clk: it's the same clock of your previous Fir

reset_n: it's active low so you've to put a not before your reset signal

ast_sink_data and ast_sink_valid are the input to the FIR Block

ast_source_ready: must be set to 1 if the block that take the FIR Block output can accept it (for example if you store the output of the fir to a Fifo you should use the NOT FULL of the fifo).

ast_sink_error: useless fix it to ground (or connect it to the ast_source_error of the block that feeds the input to your Fir).

ast_source_data & ast_source_valid: are the output data and valid of your fir block

ast_sink_ready: it's an output that indicate that the fir is able to accept new datas

10. ast_source_error: reveal if your fir has problems

Keep in mind that the new way of the IP is that all of them could be cascaded with easy and that than connect to an avalon bus also (it's from that, that they take their strange name).

Moreover try to use the graphic approac (Block Editor) and put down a Fir so it'll become more easy to understand what they're for.

Pay attention to the notation of source and sink that imo are done very bad cause they refer to different things also with the same name.

For example ast_source_ready is an input that indicate that a block following your one is ready to accept data and so your block could send data out to it.