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Altera_Forum
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13 years ago

clocked video output underflow and display flickers

Hi I'm doing a qsys design which is composed of a sdi rx, a clocked video input, a deinterlacer, an interlacer, a clocked video output, and a sdi tx. This design simply receives an interlace...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

You need additional chip, which recovers SDI clock from SDI input. That chip will provide clock to Your FPGA. And yes, You need to read more about genlock.