clocked video output underflow and display flickers

Hi Socrates

Thank you for the reply.

You really help me a lot on my SDI project.

I'm wondering how I can check whether the sdi reception clock is inaccurate.

Because I generate the sdi input video by the rtl code provided in Altera SDI example, I doubt that the timing of the sdi input may not be very accurate.

This generated sdi input video can be received by SDI receiver. I can see frame locked by checking rx_status.

But I'm not sure about if the input video is very accurate.

About the Genlock, I'm confused.

Is Genlock a technique which can be done in SDI IP or an additional chip on PCB?

I may need more time to study Genlock.

Thanks again.